For example, in a case where an asynchronous signal is mapped and transmitted to a synchronous network, an adjustment is made between the speed of the asynchronous signal and the signal transmission speed in the synchronous network, using the concept of “stuffing” (for example, refer to Japanese Laid-open Patent Publication No. 2002-217940). This signal speed adjustment based on stuffing is such that in a case of performing mapping of an asynchronous signal, when the amount of information of the asynchronous signal is low, invalid data is inserted to a predetermined stuff position with respect to the data column of the asynchronous signal, and the clock frequency corresponding to the post-mapping signal is matched with the clock frequency in the synchronous network. When the amount of information of the asynchronous signal is high, the invalid data at the above stuff position is replaced with valid data.
On the side where the signal that has been transmitted through the synchronous network is demapped, the transmitted signal is input to a destuff circuit, and a destuffing process for removing invalid data included in the input data and extracting only valid data is performed based on the information related to the stuffing insertion position, to thereby re-generate an asynchronous signal the same as that prior to transmission through the synchronous network. The stuffing insertion position is defined as a portion which is predetermined according to the mapping specification, or is found by calculation based on the overhead information of the transmission signal.
FIG. 1 is a diagram illustrating a configuration example of a generic destuff circuit that processes comparatively low-speed signals. This destuff circuit is configured with use of an elastic type FIFO (first-in first-out) 101. If the destuff circuit judges that the input data corresponds to invalid data (S1, S2 in FIG. 1) based on the information related to the stuffing insertion position in the input data to the FIFO 101, an enabling signal EN that controls data writing into the FIFO 101 to be performed according to a writing clock signal CLK-W is made a low level, and thereby data writing into the FIFO 101 is disabled. Consequently, the invalid data is removed from the input data to the FIFO 101, and valid data (D1, D2, to D6 in FIG. 1) is read out from the FIFO according to a reading clock signal CLK-R.
In the destuff circuit described above, there is employed a method where data is parallel-processed and the operating clock of the circuit is suppressed low as signals to be processed become faster (for example, refer to Japanese Laid-open Patent Publication No. 2007-336042). Specifically, as illustrated in FIG. 2 for example, parallel data signals DT1 to DT4 assigned to four lanes are input to a matrix switch 201 having four input ports and four output ports, and the matrix switch 201 performs switching operations according to control signals that are output from a switch control circuit 202 based on signals indicating a stuff position in the respective lanes, to thereby sort data within a same column to be input to the matrix switch 201 at the same timing. The parallel data signals output from the matrix switch 201 are respectively input to FIFOs 2031 to 2034 corresponding to the respective lanes, and the respective FIFOs 2031 to 2034 operate in a manner similar to that in the case of FIG. 1 described above, to thereby output parallel data signals DT1out to DT4out in which invalid data are removed and only valid data are extracted.
However, in conventional destuff circuits that parallel-process input data such as illustrated in FIG. 2 above, there is a problem in that the configuration of the matrix switch circuit that sorts data according to stuff positions becomes complex, and consequently it is difficult to perform input data sorting at high speed and the speed of a destuffing process is restricted. This problem becomes significant when the parallel number of input data becomes higher and the number of input/output ports of the matrix switch becomes higher, and it consequently makes realization of a destuff circuit capable of handling signals of even higher speed difficult.